Integrated circuit verification method

ABSTRACT

A method for verifying an integrated circuit comprising components connected by connections, the integrated circuit being defined by “physical” and “schematic” representations, comprising the steps of: establishing an annotated physical description of the circuit which enables associating with each connection of the schematic representation several polygons of the physical representation forming a track; defining at least one type of electric signal capable of propagating on the connections; defining, for each signal type, rules to be verified by each track on which the considered type of signal can propagate, specific geometric features of a given track and/or features relative to the positioning of a given track with respect to other tracks having to be verified for each rule; determining, for each connection, whether the tracks associated with the studied connections verify the rules corresponding to the signal types capable of propagating on each connection.

CLAIM FOR PRIORITY

This application claims the benefit of French Application No. 03/50833,filed Nov. 13, 2003 and is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods for verifying an integratedcircuit prior to its manufacturing.

2. Discussion of the Related Art

The manufacturing of an integrated circuit is performed based on a setof masks. Each mask generally comprises a set of polygons which enabledefining semiconductor areas, insulating areas, transistor gates,conductive tracks, and other elements of the integrated circuit. The setof masks corresponding to an integrated circuit is formed from a“physical” representation of the circuit on which are defined a set ofpolygons of various types from which it is possible to manufacture allthe masks.

The polygons defined on a physical representation of an integratedcircuit correspond to an assembly of interconnected components connectedto input/output pads by electric connections. The components and theconnections are generally explicitly defined in a “schematic”representation of the integrated circuit. Each component and eachconnection of the schematic representation corresponds to a set ofpolygons defined on the physical representation. Each set of polygonsassociated with a connection will be called a track hereafter.

FIG. 1 is an example of a schematic representation of an integratedcircuit, and more specifically of a SRAM point corresponding to a basicelement of a SRAM. The SRAM point comprises two looped inverters I1 andI2, the output of one inverter being connected to the input of the otherone. The SRAM point further comprises two NMOS access transistors Ta1and Ta2 controlled by a word line WL. Transistor Ta1 is placed betweenthe output of inverter I1 and a bit line BL. Transistor Ta2 is placedbetween the output of inverter 12 and a bit line BLN.

FIG. 2 is a schematic representation of an inverter such as inverters I1and I2. An inverter comprises a PMOS transistor P1 and an NMOStransistor N1 in series between a power supply Vdd and a ground GND. Thegates of transistors P1 and N1 are connected to an input pad A. Thedrains of transistors P1 and N1 are connected to an output pad Z.

FIG. 3 is an example of a physical representation of a SRAM pointcorresponding to the above-described electric representation. Thisphysical representation substantially corresponds to a top view of theintegrated circuit masks such as it could be seen on a display screenand thus, what is at the top of the drawing is above what is at thebottom of the drawing. Similarly, what is described as being horizontalor vertical refers to an on-screen representation. Such considerationswill be valid for all the physical representations described hereafter.Each transistor is represented by an active area and a gate areaintersecting perpendicularly. Metal areas enable interconnecting activeareas and/or gate areas.

Two rectangular active areas 1 and 2 are placed horizontally, area 1being at the top and area 2 at the bottom of FIG. 3. Two rectangularactive areas 3 and 4 are placed horizontally on each side of active area2. Two gate areas 5 and 6 substantially having the shape of verticaltracks cut active areas 1 and 2 perpendicularly, areas 5 and 6 beingrespectively placed to the left and to the right. Two gate areas 7 and 8substantially having the shape of short vertical tracks cut active areas3 and 4. Active area 1 is P-type doped and active areas 2, 3, and 4 areN-type doped.

The portion of active area 1 located between gate areas 5 and 6 formsthe source of the PMOS transistors of each of inverters I1 and I2. Theportions of active area 1 located on either side of gate areas 5 and 6form the drains of the PMOS transistors of inverters I1 and I2.Similarly, the portion of active area 2 located between gate areas 5 and6 forms the source of the NMOS transistors of each of inverters I1 andI2. The portions of active area 2 located on either side of gate areas 5and 6 form the drains of the NMOS transistors of inverters I1 and I2.The portions of active areas 3 and 4 located on either side of gateareas 7 and 8 form source/drain areas of access transistors Ta1 and Ta2.

Two rail-shaped horizontal metal areas 10 and 11 are respectively placedabove and under active areas 1, 2, 3 and gate areas 5, 6, 7, and 8.Areas 10 and 11 are intended to be respectively connected to powersupply Vdd and to ground GND. A metal area 12 connects track 10 (Vdd) tothe portion of active area 1 forming the source of the PMOS transistors.A metal area 13 connects track 11 (GND) to the portion of active area 2forming the source of the NMOS transistors. A metal area 14 connects theleft-hand portions of active areas 1 and 2 corresponding to drain areas.Similarly, a metal area 15 connects the right-hand portions of activeareas 1 and 2 corresponding to drain areas. Two metal areas 16 and 17connect metal areas 14 and 15 respectively to gate areas 6 and 5. Ametal area 18 connects the portions of active source/drain areas 2 and 3located next to each other. Similarly, a metal area 19 connects theportions of active source/drain areas 2 and 4 located next to eachother. The lateral portions of active areas 3 and 4 are respectivelyconnected to two metal areas 20 and 21 corresponding to bit lines BL andBLN. Gate areas 7 and 8 are respectively connected to two metal areas 22and 23 corresponding to word lines WL and WLN. Each connection between ametal area and an active area or a gate area is ensured by a conductivevia represented by a cross placed in a square.

The existing methods for verifying an integrated circuit defined by aphysical representation and a schematic representation such as describedhereabove generally comprise the next three steps.

A first step consists of verifying the circuit functionality, this beinggenerally performed by means of an electric simulation performed basedon the schematic representation of the circuit. In an electricsimulation, a series of states corresponding to a series of stimuliapplied on the circuit inputs is defined based on an initial electricstate of the circuit. For each state of the circuit, the electricvoltage, or the logic level “0” or “1”, of each of the circuitconnections, is defined. If necessary, especially in the case ofso-called “analog” circuits, the value of the input or output currentsof each of the circuit components is also determined. The analysis ofthe series of circuit states obtained after simulation enables verifyingthe circuit functionality.

A second step consists of verifying that the circuit such as defined bythe physical representation fulfils all manufacturing constraints. Thissecond step gathers several verifications known as DRC, DFM, and ERC(Design Rule Check, Design For Manufacturing, and Electrical Rule Check)and mainly consists of verifying the geometric features of each polygon(width, surface area, . . . ) and the intervals between the variouspolygons of the physical representation of the circuit.

A third step, known as the LVS step (Layout Versus Schematic), consistsof verifying that all the polygons of the physical representationactually correspond to the components and connections of the schematicrepresentation. For this purpose, a first list of components and ofconnections is “extracted” from the physical representation byperforming a recognition of polygon groups, each corresponding either toa known component type, or to a connection. As an example, theassociation of a perpendicularly-intersecting active area and of gatearea is recognized as defining a transistor. In parallel, a second listof components and of connections is established based on the schematicrepresentation. It is then verified that the two lists do comprise thesame components and identical connections between the variouscomponents.

Such existing integrated circuit verification methods do not enabledetecting certain weaknesses of a circuit manufactured according to themost recent methods. The possibly weaknesses of a “modern” circuit areof various natures and each type of weakness generates a malfunction ofthe circuit in specific circuit use conditions. When the circuit is usedin conditions likely to “reveal” certain weaknesses of the circuit, themost current phenomena that can occur at the circuit level are thefollowing.

A known phenomenon is the electromigration of one or several metal areaswhich generally results in a cutting of the metal tracks. The potentialtrack electromigration risks are all the greater as the size and thecomplexity of the circuits is greater. No circuit verification methodenables detecting areas at risk. Only the designer's vigilance can avoidthis type of problem.

Another known phenomenon is the modification of the voltage, in otherwords, a state switching, of a metal track due to a stray capacitivecoupling between two metal tracks.

Another known phenomenon is the local supply voltage decrease, inportions of a circuit where many components simultaneously conductstrong electric currents, the voltage decrease being proportional to thetotal requested current and to the resistance of the supply tracks. Thisphenomenon is generally observed in so-called synchronous circuits forwhich the latch registers all switch at the same moment. A localdecrease in the power supply results in a poor operation of theunder-supplied cells.

Certain weak areas likely to cause the occurrence of the last twoabove-mentioned phenomena can be partially detected by performing anelectric simulation of the circuit based on a “improved” schematicrepresentation comprising parasitic components (resistors, capacitors,coils) determined from the physical representation of the circuit andespecially from all the conductive areas corresponding to the variousconnections defined in the schematic representation. However, currentmethods for extracting all these parasitic components do not enabledetermining with a sufficient accuracy the resistive, capacitive, andinductive values of the parasitic components, and this, all the more asthe circuit size is large and as the physical representation isorganized in several hierarchical levels. Further, the size of the“improved” schematic representation obtained after extraction of theparasitic components is generally from two to three times as high as theschematic base representation and its electric simulation may be verylong and require many computer resources. The simulation difficulty thenresults in limiting the number of tested stimuli, which stronglydecreases the possibilities of detecting possible weaknesses. Further,even if wide hardware and time resources are available, the definitionof “exhaustive” stimuli enabling testing all the cases of use oftenappears to be impossible.

The above-mentioned problems appear when a metal track has a shape or apositioning with respect to the other tracks which is inappropriate toits use. A problem may occur on a track, for example, in the case wherethe current density running through it is too high or in the case wherethe frequency of the electric signal running through it or runningthrough a close track is too high.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method for verifyingan integrated circuit, which is capable of rapidly verifying that eachmetal track has geometric features and/or a positioning with respect tothe other tracks adapted to its use.

To achieve this object, the present invention provides a method forverifying an integrated circuit comprising components connected byconnections, the integrated circuit being defined by a “physical”representation and a “schematic” representation, the physicalrepresentation consisting of an assembly of polygons of various typesused to form a set of masks used for the integrated circuitmanufacturing, the schematic representation symbolically defining thecircuit components and the connections between these components, themethod comprising the steps of: establishing an annotated physicaldescription of the circuit which enables associating with eachconnection of the schematic representation a set of polygons of thephysical representation forming a track; defining at least one type ofelectric signal capable of propagating on the various circuitconnections; defining, for each signal type, one or several rules to beverified by each of the tracks corresponding to the connections on whichthe considered type of signal is capable of propagating, specificgeometric features of a given track and/or features relative to thepositioning of a given track with respect to other tracks having to beverified for each rule; determining, for all or part of the connections,whether the tracks associated with the studied connections verify therule(s) corresponding to the signal types capable of propagating on eachof the connections.

The foregoing object, features, and advantages, as well as others of thepresent invention will be discussed in detail in the followingnon-limiting description of specific embodiments in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation, previously described, of a SRAMpoint;

FIG. 2 is a schematic representation, previously described, of aninverter;

FIG. 3 is a physical representation, previously described, of the SRAMpoint of FIG. 1;

FIG. 4 is a physical representation of an inverter;

FIG. 5 is a physical representation of an NMOS transistor;

FIG. 6 is a schematic representation of a MOS transistor;

FIG. 7 is a hierarchical physical representation of a SRAM point;

FIG. 8 is a perspective view of a track;

FIG. 9 is a perspective view of a track;

FIG. 10 is a perspective view of a track;

FIG. 11 is an equivalent electric diagram of the track shown in FIG. 10;and

FIG. 12 is a top view of two tracks.

DETAILED DESCRIPTION

The method of the present invention enables, from a physicalrepresentation and a schematic representation of an integrated circuit,verifying the specific geometric features of a track and/or thepositioning features of a track with respect to the positionings ofother tracks according to the type of electric signal capable ofpropagating on the studied track. To perform such a verification, themethod of the present invention comprises several steps definedhereafter.

1. Annotated Physical Description

A first step consists of establishing an annotated physical descriptionof the circuit from which it is possible to associate with eachconnection of the schematic representation of the circuit a track formedof one or several polygons of the physical representation. Thedefinition of an annotated physical description of a circuit isspecified hereafter based on a very simple circuit example, an inverter,and then based on a more complicated “hierarchical” circuit example.

1.1. Annotated Physical Description of a Simple Circuit

FIG. 4 is a physical representation of an inverter corresponding to theschematic representation of FIG. 2. Two rectangular active areas p1 andp2 are placed horizontally one above the other, area p1 being on top. Agate area p3 substantially having the shape of a vertical track cutsactive areas p1 and p2 perpendicularly. The portions of active areas p1and p2 uncovered by gate area p3 are respectively P- and N-type doped. Avertical metal area p4 connects the portions of active areas p1 and p2located to the right of gate area p3. A short horizontal metal area p5is substantially connected to the middle of gate area p3. Metal area p5forms the input terminal of the inverter, metal area p4 forming theoutput terminal. Two short vertical metal areas p6 and p7 arerespectively connected to the portions of active areas p1 and p2 locatedto the left of gate area p3. Metal areas p6 and p7 are intended to berespectively connected to power supply Vdd and to ground GND. Thevarious metal areas are connected to the active or gate areas by aconductive via shown by a cross in a square. Further, the metal areasare in this physical representation all formed on the same integratedcircuit metallization level and more specifically on the first metallevel “métal1” placed immediately above the active components formed inthe semiconductor substrate of the integrated circuit.

The physical representation of an integrated circuit is generallyobtained by means of a computer device. The physical representationsdisplayed on the screen of the computer device are substantially thoseshown in FIGS. 3 and 4. The polygons of the physical representation aredescribed in one or several computer files. The file(s) describing eachof the polygons form a physical description of the circuit.

In a conventional physical description of a circuit, each polygon isdefined by a series of coordinates of the points defining the polygonand a “type” indicating whether the polygon is in an active area, a gatearea, a metal area, or other. In the example of the inverter shown inFIG. 4, a conventional physical description is given in the followingtable I. The coordinates of the points defining the polygons are given,in this example, in a Cartesian referential.

-   -   p1: (0;8)(4;8)(4;10)(0;10)-active    -   p2: (0;1)(4;1)(4;3)(0;3)-active    -   p3: (2;0.5)(3;0.5)(3;10.5)(2;10.5)-gate    -   p4: (3.25;1.25)(3.75;1.25)(3.75;9.75)(3.25;9.75)-métal1    -   p5: (1.5;5.25)(2.75;5.25)(2.75;5.75)(1.5;5.75)-métal1    -   p6: (0.5;8.5)(1.5;8.5)(1.5;11)(0.5;11)-métal1    -   p7: (0.5;0)(1.5;0)(1.5;2.5)(0.5;2.5)-métal1

The first step of the method of the present invention aims atestablishing an “annotated” physical description of the circuit whichcontains additional elements with respect to a current description suchas defined hereabove. The additional elements aim at indicating whethera given polygon corresponds to one of the connections defined in theschematic circuit representation.

In the example of an inverter, the description given hereabove isannotated according to the following table II:

-   -   p1: (0;8)(4;8)(4;10)(0;10)-active    -   p2: (0;1)(4;1)(4;3)(0;3)-active    -   p3: (2;0;5)(3;0.5)(3;10.5)(2;10.5)-gate    -   p4: (3.25;1.25)(3.75;1.25)(3.75;9.75)(3.25;9.75)-métal1-Z    -   p5: (1.5;5.25)(2.75;5.25)(2.75;5.75)(1.5;5.75)-métal1-A    -   p6: (0.5;8.5)(1.5;8.5)(1.5;11)(0.5;11)-métal1-Vdd    -   p7: (0.5;0)(1.5;0)(1.5;2.5)(0.5;2.5)-métal1-GND

Based on this annotated physical description, it is possible toassociate with each connection of the schematic representation of theinverter a track of the physical representation. In the examplehereabove, each track corresponds to a single polygon, or in other wordsto a single metal area. However, in more complex circuits, a track isgenerally formed of several polygons.

An annotated physical description of a circuit may be obtained accordingto various methods.

One method consists of defining from as soon as the creation of apolygon the connection to which it corresponds. This method is inpractice possible to envisage only for very simple circuits such as theabove-described inverter.

Another method consists of initially creating a physical representationand an associated conventional physical description which contains noconnection information or which only contain some for part of thepolygons. A first list of components and of connections between thesecomponents based on the physical representation of the circuit is thenextracted. The components and the connections defined in this first listhave arbitrary names. It is defined, in an association file, to whichset of polygons each component and each connection of the first listcorresponds, the polygon(s) corresponding to a connection forming atrack. In parallel, a second list of components and connections isestablished from the schematic representation. The correspondencesbetween the components and the connections of the two lists are thendetermined according to known methods especially used in verificationmethods known as LVS. By means of the association file, it is thendetermined to which connection of the schematic representation eachtrack and, by extension, each of the track polygons corresponds.

This method enables performing an automatically-annotated description.As compared with the first mentioned method, it enables saving time upondesign of the physical representation of the circuit. This second methodmay in particular be used when the circuit has a significant size.

1.2. Annotated Physical Description of a Hierarchical Circuit

An example of a hierarchical circuit is given hereafter. The physicalrepresentation of a hierarchic circuit is constructed from “basic”bricks. Each basic brick is a physical representation of an elementgenerally used several times in the complete physical representation.

FIGS. 5 and 6 respectively are a physical representation of an NMOStransistor and a schematic representation of this transistor. Thephysical representation comprises a rectangular and horizontal activearea p10, a rectangular and vertical gate area p1 perpendicularlycutting active area p10, as well as three metal areas p12, p13, and p14respectively connected to the portion of active area p10 located to theright of gate area p1, to the portion of gate p1 and to the portion ofactive area p10 located to the left of gate area p1. Metal areas p12,p13, and p14 are all formed on the first available metal level “métal1”.The schematic representation comprises a transistor T having its gateconnected to a connection or terminal G, and the source/drain areas areconnected to connections E1 and E2.

FIG. 7 is a hierarchical physical representation of a SRAM pointconstructed based on two basic bricks: the inverter and the NMOStransistor respectively shown in FIGS. 4 and 5. The memory pointcomprises two replicas X1 and X2 of the inverter and two replicas X3 andX4 of the NMOS transistor. As known by those skilled in the art, from acomputer point of view, each replica is generally a virtual copy of thephysical representation of a basic brick. In practice, the physicalrepresentation of the inverter is described only once in the computerfile and the physical representation of each replica is obtained byreading of the description of the “copied” object. Replicas X1, X3, andX4 are placed on the physical representation of the SRAM point with anorientation identical to the orientation of the corresponding basicbrick. Replica X2 of the inverter is however placed on the physicalrepresentation of the SRAM point after having undergone a transformationcorresponding to the creation of the symmetrical of the physicalrepresentation of the inverter with respect to a vertical straight linesuperposing with the left-hand vertical sides of active areas p1 and p2.Replicas X1 and X2 appear as being partially superposed so that tracksp6 (or p7) of each replica are perfectly superposed. The superpositionof two tracks of the same type finally forms a single track. As forreplicas X3 and X4, they are respectively placed to the left of replicaX2 and to the right of replica X3.

The memory point further comprises metal areas positioned so that a“flat laying” of the entire hierarchical physical representation of thismemory point would provide the physical representation of FIG. 3. Twohorizontal metal areas p20 and p21 are placed respectively above andunder replicas X1 to X4, like areas 10 and 11 of the “flat laid”physical representation of FIG. 3. Two metal areas p22 and p23, havingshapes respectively identical to areas 16 and 17, are placed to connecttrack p4 of an inverter to the area p5 of the other inverter. Twohorizontal metal areas p24 and p25 are placed to respectively connectarea p4 of inverter X2 to area p12 of transistor X3 and area p4 ofinverter X1 to area p14 of transistor X4. Metal areas p22 to p25 areformed on a first metal level “métal1”. A horizontal metal area p26,partially shown, is placed on a second metal level “métal2” above areasp13 of transistors X3 and X4 to which it is connected by two conductivevias represented by a cross in a square. Similarly, two vertical metalareas p27 and p28, partially shown, are placed on a third metal level“métal3” respectively above track p14 of transistor X3 and track p10 oftransistor X4. Areas p27 and p28 are respectively connected to areas p14of X3 and p10 of X4 by two superposed conductive vias represented by across in a square.

Generally, the physical description of a hierarchical circuit indexes ina file or in a file portion the different positioned replicas and allthe areas and tracks added to the replicas. The physical description ofthe replicated elements is generally performed only once in separatedfiles or in different parts of a same file possibly containing thephysical description of the circuit in which the replicas are placed.The physical description of a replicated element indexes areas andpossibly a replica of another element in the case where there are morethan two hierarchical levels.

In the above-described SRAM point example, 3 files or file portions areused to describe the inverter, the transistor and the memory point,respectively shown in FIGS. 4, 5, and 7. The annotated physicaldescription of the inverter is identical to that given hereabove intable I.

The annotated physical description of the transistor corresponding tothe physical and schematic representations of FIGS. 5 and 6 is given inthe following table III:

-   -   p10: (0;0.5)(3;0.5)(3;2.5)(0;2.5)-active    -   p11: (1;0)(2;0)(2;4.5)(1;4.5)-gate    -   p12: (2.25;1)(2.75;1)(3;2)(2.25;2)-métal1-E2    -   p13: (1.25;3.5)(1.75;3.5)(1.75;4)(1.25;4)-métal1-G    -   p14: (0.25;1)(0.75;1)(0.75;2)(0.25;2)-métal1-E1

A conventional physical description of the SRAM point corresponding tothe physical and schematic representations of FIGS. 1 and 6 is given inthe following table IV:

-   -   X1: inverter replica-(6;1)    -   X2: inverter replica-vertical symmetry-(4;1)    -   X3: transistor replica-(0;1.5)    -   X4: transistor replica-(11;1.5)    -   p22: (4.75;7.5)(7.25;7.5)(7.25;6.25)(7.75;6.25)(7.75;8)        (4.75;8)-métal1    -   p23:        (6.25;5)(9.25;5)(9.25;5.5)(6.75;5.5)(6.75;6.75)(6.25;6.75)-métal1    -   p24: (2.25;1.75)(4.75;1.75)(4.75;2.25)(2.25;2.25)-métal1    -   p25: (9.25;1.75)(11.75;1.75)(11.75;2.25)(9.25;2.25)-métal1    -   p26: (0;5)(14;5)(14;5.5)(0;5.5)-métal2    -   p27: (0.25;0)(0.75;0)(0.75;13)(0.25;13)-métal3    -   p28: (13.25;0)(13.75;0)(13.75;13)(13.25;13)-métal3

An annotated physical description of the SRAM point is given in thefollowing table V:

-   -   p22: (4.75;7.5)(7.25;7.5)(7.25;6.25)(7.75;6.25)(7.75;8)        (4.75;8)-métal1-C2    -   p23:        (6.25;5)(9.25;5)(9.25;5.5)(6.75;5.5)(6.75;6.75)(6.25;6.75)-métal1-C1    -   p24: (2.25;1.75)(4.75;1.75)(4.75;2.25)(2.25;2.25)-métal1-C1    -   p25: (9.25;1.75)(11.75;1.75)(11.75;2.25)(9.25;2.25)-métal1-C2    -   p26: (0;5)(14;5)(14;5.5)(0;5.5)-métal2-WL    -   p27: (0.25;0)(0.75;0)(0.75;13)(0.25;13)-métal3-BLN    -   p28: (13.25;0)(13.75;0)(13.75;13)(13.25;13)-métal3-BL    -   X1: inverter replica-(6;1)-C2:Z, C1:A, Vdd:Vdd, GND:GND    -   X2: inverter replica-vertical symmetry-(4;1)-C1:Z, C2:A,        Vdd:Vdd, GND:GND    -   X3: transistor replica-(0;1.5)-C2:E2, BLN:E1, WL:G    -   X4: transistor replica-(11;1.5)-C1:E1, BLN:E2, WL:G

In the line relative to replica X1, C2:Z means that the area associatedwith connection Z in the inverter prolongs the areas associated withconnection C2 in the memory point. Similarly, C1:A means that the areaassociated with connection A in the inverter prolongs the areasassociated with connection C1 in the memory point. Notations Vdd:Vdd andGND:GND mean that the area associated with connection Vdd or GND in theinverter prolong the area associated with connection Vdd or GND in thememory point. The notations used for the other replicas are identical.

Based on the connection information given in each of the annotatedphysical descriptions, it is possible to find to which connectioncorresponds each of the metal areas defined on the various hierarchicallevels, each area assembly associated with a connection forming a track.

An annotated physical description of a circuit with a hierarchicalphysical description may be obtained according to various methodssubstantially identical to those mentioned hereabove in the precedingpart.

2. Signal Types and Associated Rules—Verifications

After having created an annotated description of the studied circuitwhich enables associating with each connection of the schematicrepresentation of the circuit a track of the physical representation ofthe circuit, the following steps of the method of the present inventionaims at verifying that each track is adapted to its use.

Each track is used to propagate one or several types of electric signalswhich can be determined by the circuit designer. Each type of signal maybe described by a time representation of the electric potential of aconnection and/or of the current flowing through a connection. The mostcurrent signal types are the following:

-   -   a signal of “steady” type for which the voltage is substantially        constant along time.    -   a signal of “clock” type, for which the voltage periodically        varies from low level “0” to high level “1”, each level        switching being performed rapidly, that is, with a steep edge.    -   a signal of “HF” type, for which the voltage varies rapidly        along time.    -   a signal of “random” type, for which the voltage changes        according to the circuit activity.    -   a signal of “current peak” type, for which at given times, the        current reaches a very high value.    -   a signal of “strong current” type, for which a substantially        high current is observed for a relatively long time.

The above-described signal types are given as an indication. Many othersignal types may be devised by those skilled in the art.

Further, a given track may be used to propagate signals of varioustypes. A track conducting the supply voltage propagates a signal of“steady” type, but may also propagate a signal of “current peak” or“strong current” type especially according to the circuit activity.

Further, the types of signals capable of propagating on the variouscircuit connections may be determined on functional verification of thecircuit performed by means of an electric simulation.

The types of signals finally studied will in fact be defined accordingto the problems that the circuit designer wishes to detect. Forelectromigration problems, signals of “current peak” or “strong current”type will especially be considered. For voltage drop problems, signalsof “steady” type will rather be considered, especially to verify thecircuit supply network. For stray capacitive coupling problems, signalsof “clock” or “HF” type will be considered.

Once the signal type(s) which are desired to be studied have beendetermined, it is set for each signal type what rules must be verifiedby the circuit tracks corresponding to the connections on which theconsidered signal type is capable of propagating. Examples of rules aregiven hereafter in the case where electromigration, voltage drop, orstray capacitive couplings problems are desired to be detected.

In the case of the electromigration problem, it is desired to determinewhether the tracks corresponding to connections on which signals of“current peak” or “strong current” type are capable of propagating aresufficiently “wide”. In other words, it is desired to determine whetherat any point of the considered track, the current density is not toohigh.

FIG. 8 is a perspective view of a track formed of three successive metalareas p50, p51, and p52 placed on a same metallization level. The areasall have the same thickness, as current in integrated circuits. Areasp50 and p52 are relatively wide and area p51 connecting the two otherareas is relatively narrow.

FIG. 9 is a perspective view of another track formed of two relativelywide metal tracks p60 and p61 placed on two adjacent metal levels, areap61 being placed on the lower level. A relatively thin conductive viap62 connects an end of area p60 to an end of area p61.

In the two above-mentioned examples, there clearly appears that narrowarea p51 and conductive via p62 are the track elements through which thecurrent density risks to be high. A track end much narrower than therest often is a design error which can be relatively often encounteredin a hierarchical circuit when it is not always easy to visualize allthe track areas belonging to different hierarchical levels. The presenceof a single relatively narrow conductive via between metal areas placedon adjacent levels also is a relatively current design error.

A possible rule of verification of the tracks corresponding toconnections on which signals of “current peak” or “strong current” typeare capable of propagating is the following. The ratio of thecross-section areas of two consecutive areas of a track must not begreater than or smaller than predetermined threshold values. Thethreshold values are set according to technological parameters such asthe type of material and its resistance.

In the case of the voltage drop problem, it is desired to determinewhether the tracks corresponding to connection on which signals of“steady” type are capable of propagating are not too resistive.

FIG. 10 is a perspective view of a track intended to propagate thecircuit supply voltage. The track comprises a metal area p70 for exampleplaced on a second metallization level and four metallization areas p71,p72, p73, and p74 placed on a first metallization level. Area p71substantially has the shape of a rail. An end of area p70 is connectedto an end of area p71 by a conductive via p75. Areas p72, p73, and p74,of same lengths, are placed at regular intervals against area p71perpendicularly thereto, track p72 being the closest to conductive viap75. The end of area p70 unconnected to via p75 is connected to a supplyterminal. The supply voltage then propagates through the conductive viato the end of areas p71 to p74.

FIG. 11 is an equivalent electric diagram of the track shown in FIG. 10.Each area or area portion can be modeled by a resistor. Area p70 has anequivalent resistance R70, the conductive via has an equivalentresistance R75. Rail-shaped area p71 is cut into four areas p71 a, p71b, p71 c, and p71 d starting from the conductive via, the limits betweenthese areas being placed in prolongation of areas p72, p73, and p74.Areas p71 a, p71 b, p71 c, and p71 d respectively have equivalentresistances R71 a, R71 b, R71 c, and R71 d. Areas p72, p73, and p74 haveequivalent resistances R72, R73, and R74. On the equivalent electricdiagram of the track, resistors R70, R75, R71 a, R71 b, R71 c, and R71 dare placed in series between a terminal A through which the circuit issupplied and a terminal C1 connected to a circuit component not shown.Resistors R72, R73, and R74 each have a terminal respectively connectedbetween R71 a/R71 b, R71 b/R71 c, and R71 c/R71 d. The free terminals ofresistors R72, R73, and R74 are respectively called C2, C3, and C4 andare connected to components not shown. Areas p72, p73, and p74 being ofsame lengths, resistors R72, R73, and R74 are identical.

Considering that each of the components connected to terminals C1 to C4is likely to conduct an identical current, and knowing that the voltagedrop across a resistor is proportional to its resistance and to thecurrent flowing therethrough, there clearly appears that a maximumsupply voltage drop can be detected at the level of terminals C1 and C4.

A possible rule for verifying the tracks corresponding to connections onwhich signals of “steady” type are capable of propagating is thefollowing. The equivalent resistance between a “starting point” and an“end point” of the track, along which the signal propagates, must besmaller than a predetermined value.

In the case of the problem of stray capacitive couplings, it is desiredto determine whether the tracks capable of propagating signals of“clock” or “HF” type are not too close to other tracks of the circuit,which could induce a state switching of these other tracks, or anadvance or a delay of the signal propagating on these other tracks.

FIG. 12 is a top view of two tracks p80 and p81 placed on a samemetallization level. Track p80 is rectilinear and appears to behorizontal in FIG. 12. Track p81 is placed close to track p80substantially parallel to the latter. Track p81 is substantially formedof three successive rectilinear portions p81 a, p81 b, and p81 cappearing as being horizontal. The two portions p81 a and p81 c areplaced at each end on the same axis. Portion p81 b, in contact with theother portions p81 a and p81 c, is shifted to the side of track p80.

The stray capacitance between the two tracks being inverselyproportional to the spacing between tracks, the proximity of track p80and of track portion p81 b strongly contributes to creating anon-negligible stray capacitance between tracks p80 and p81. Further,the stray capacitance between two tracks is proportional to theiropposite surface areas. In this example, the stray capacitance betweentracks p80 and p81 is substantially proportional to length d of trackportion p81 b.

A possible rule for verifying the tracks corresponding to connections onwhich signals of “HF” or “clock” type are capable of propagating is thefollowing. It is first searched whether a circuit track is “close” tothe studied track, that is, if the spacing between the studied track andanother circuit track is smaller than a predetermined distance. Finally,in the case where all or part of a track is close to the studied track,the opposite surface area between these two tracks is evaluated todetermine the stray capacitance between these tracks. The calculatedstray capacitance must then be smaller than a predetermined value.

In parallel or after the laying down of the rules to be verified by eachof the types of signals which are desired to be studied, which are thesignal type(s) capable of propagating on the circuit connections whichare desired to be verified is determined. It is then verified whethereach track corresponding to a connection which is desired to be studiedverifies the rules corresponding to the signal types capable ofpropagating on the considered connection.

At the end of this verification, the physical representation of thecircuit may be displayed and the tracks likely to exhibit a technicaldefect may be highlighted. An advantage of the present invention isthat, due to the annotated physical description, it is possible torapidly and easily identify the set of polygons of a defective track.Thus, in the case where the physical representation of the circuitcomprises a large number of hierarchical level, it is possible tohighlight the set of polygons of a track placed on differenthierarchical levels.

Further, the verification method according to the present invention maybe implemented on a small circuit portion without it being necessary toextract the circuit parasitic components. Further, it is not necessaryto perform an electric simulation of the entire circuit, requiring largecomputer resources. Once the annotated physical representation has beenformed, the various circuit portions may advantageously be verified inparallel. This enables performing an analysis within a very short time.

Of course, the present invention is likely to have various, alterations,improvements, and modifications which will readily occur to thoseskilled in the art. In particular, it may be attempted to detectproblems different from those mentioned hereabove. Further, differentrules of verification of the tracks corresponding to connections onwhich signals of a given type are capable of propagating may beprovided. Further, those skilled in the art may define other types ofsignals capable of propagating over a circuit connection.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A method for verifying connections of an integrated circuitcomprising components connected by said connections, the integratedcircuit being defined by a “physical” representation and a “schematic”representation, the physical representation consisting of an assembly ofpolygons of various types used to form a set of masks for manufacturingthe integrated circuit, the schematic representation symbolicallydefining the circuit components and the connections between thesecomponents, the method comprising the steps of: establishing anannotated physical description of the circuit which enables associatingwith each of said connections of the schematic representation a set ofpolygons from the assembly of polygons of the physical representationthat corresponds to a considered connection, each set of polygonsassociated with each of said connections forming a track; and analyzingthe tracks corresponding to said connections to be verified, by:defining at least one type of electric signal capable of propagating onsaid connections; defining, for each signal type, one or several rulesto be verified by each of the tracks corresponding to the connections onwhich said electric signal is capable of propagating, specific geometricfeatures of a given track or features relative to the positioning of agiven track with respect to other tracks having to be verified for eachrule; and determining, for each of said connections to be verified,whether the tracks associated with said connections verify the one orseveral rules corresponding to the signal types capable of propagatingon each of said connections; wherein at least one signal type refers toat least one of an intensity value and a time variation of an intensityof a current running through a given connection, and wherein a rule tobe verified by each of the tracks corresponding to the connectionconsists of verifying that a ratio of cross-sectional areas ofintegrated circuit areas corresponding to two consecutive polygons of atrack ranges between two predetermined values.
 2. A method for verifyingthe connections of an integrated circuit comprising components connectedby said connections, the integrated circuit being defined by a“physical” representation and a “schematic” representation, the physicalrepresentation consisting of an assembly of polygons of various typesused to form a set of masks to be used for manufacturing the integratedcircuit, the schematic representation symbolically defining the circuitcomponents and the connections between these components, the methodcomprising the steps of: establishing an annotated physical descriptionof the circuit which enables associating with each of said connectionsof the schematic representation a set of polygons from the assembly ofpolygons of the physical representation that corresponds to a consideredconnection, each set of polygons associated with each of saidconnections forming a track; and analyzing the tracks corresponding tosaid connections to be verified, by: defining at least one type ofelectric signal capable of propagating on said connections; defining,for each signal type, one or several rules to be verified by each of thetracks corresponding to the connections on which said electric signal iscapable of propagating, specific geometric features of a given track orfeatures relative to the positioning of a given track with respect toother tracks having to be verified for each rule; and determining, foreach of the connections to be verified, whether the tracks associatedwith these connections verify the one or several rules corresponding tothe signal types capable of propagating on each of said connections;wherein at least one signal type refers to a voltage substantiallysteady along time on a given connection, and wherein a rule to beverified by each of the tracks corresponding to said connectionsconsists of verifying that an equivalent resistance of areas of theintegrated circuit corresponding to all or part of a considered track isnot greater than a predetermined value.
 3. A method for verifying theconnections of an integrated circuit comprising components connected bysaid connections, the integrated circuit being defined by a “physical”representation and a “schematic” representation, the physicalrepresentation consisting of an assembly of polygons of various typesused to form a set of masks to be used for manufacturing the integratedcircuit, the schematic representation symbolically defining the circuitcomponents and the connections between these components, the methodcomprising the steps of: establishing an annotated physical descriptionof the circuit which enables associating with each of said connectionsof the schematic representation a set of polygons from the assembly ofpolygons of the physical representation that corresponds to a consideredconnection, each set of polygons associated with each of saidconnections forming a track; and analyzing the tracks corresponding tosaid connections to be verified, by: defining at least one type ofelectric signal capable of propagating on said connections; defining,for each signal type, one or several rules to be verified by each of thetracks corresponding to the connections on which said electric signal iscapable of propagating, specific geometric features of a given track orfeatures relative to the positioning of a given track with respect toother tracks having to be verified for each rule; and determining, foreach of said connections to be verified, whether the tracks associatedwith these connections verify the one or several rules corresponding tothe signal types capable of propagating on each of the connections;wherein at least one signal type refers to a fast time variation of anelectrical potential of a given connection, and wherein a rule to beverified by each of the tracks corresponding to the connections consistsof verifying whether a portion of said considered track is located closeto another track with a distance smaller than a predetermined value, andif such is the case, verifying whether a stray capacitance between theconsidered track and other tracks is greater than a predefined maximumvalue.